A frame structure suitable for wide-band code division multiple access signal transmission features that a time-sharing multiplexing frame structure for dedicated physical control channel and dedicated physical data channel is used in forward link. Each frame is composed of 16 time slots, each being 0.625 ms. Each time slot contains pilot sign, function control sign, transmission speed indication and data. Several pilot signs are uniformly inserted in each time slot.
一种适用于宽带码分多址信号传输的帧结构，其是在前向链路中采用了专用物理控制信道和专用物理数据信道时分复用的帧结构，每帧由16个时隙构成，每个时隙为0.625毫秒，其中又包括导频符号、功控符号、传输速率指示和数据，其特征在于：在每个时隙中均匀分散插入有若干个导频符号。
In the case where a correlation value between the copying preventive control signal which is superimposed on the image signal Si and is spectrum-spread and a PN code for inverse spreading does not exceed a predetermined threshold value, the correlation value calculated at every vertical section is added.
在叠加在该图象信号Si上的并且扩频的防止复制控制信号与用于反扩展的PN码之间在的相关值不超过预定的阈值的情况下，加上在每个垂直部分计算的相关值。
SMU signal analyzer, REMOTE control the use of the initialization code and header files.
详细说明：SMU信号分析仪，REMOTE控制要用到的初始化代码和头文件。
We designed the driven-pulse generator module whose focusing delay, pulse width, pulse repetition frequency can be dynamically controlled by pre-computed codes. Also we achieved linear scanning control and probe impulse control and function code storage and other system functions both in a signal FPGA chip. Both the function simulation and timing simulation results of this sub-system show that it lays a good foundation on building high speed, high precision, fully digitalized, highly integrated modern medical ultrasonic diagnostic equipments. This paper will help to the researching and producing process. It is fresh air to the biomedical electronics, medical instrument, and medicine ultrasonic.
在单片FPGA 芯片内部设计实现了聚焦延时、脉宽和重复频率可动态控制的发射驱动脉冲产生器、线扫控制、探头激励控制、功能码存储等功能模块，功能仿真和时序分析结果表明该子系统为设计实现高速度、高精度、高集成度的全数字化超声诊断设备打下了良好的基础，将加快其研发和制造进程，为生物医学电子、医疗设备和超声诊断等方面带来新思路。
The system consists of two real-time signal-processing boards of DSP+FPGA mechanism. It implements processing of signals from SSR responder, such as anti- garble, defruiting, calculation of azimuth and range, decoding of height and special -code of planes. The system can produce inquiring-code for air traffic control and report stat...
该系统基于 2块DSP +FPGA模式的实时信号处理板，实现了对原始二次监视雷达应答信号的各种处理：反同步窜扰处理，反非同步窜扰处理，计算目标的方位、距离，进行目标的高度、代号解码以及实时产生航管询问编码，并生成各种信息的统计报告。
The introductive robot arm of this text can output two lines pulses by the PLC, driving the horizontal stalk, and the perpendicular stalk to drive the electrical engineering actuator respectively, to control the robot arm precision of the horizontal stalk and perpendicular stalk at the fixed position, tiny move switch input the position signal to the PLC. The direct current motor drags along to begin the claw and bedrocks to revolve, the position signal from revolve the code dish and near to the switch feedback to host of PLC; The electromagnetism valve control the machine hand open and close, thus carry out the function of the machine hand precision work.
本文介绍的机械手是由PLC输出两路脉冲，分别驱动横轴、竖轴步进电机驱动器，控制机械手横轴和竖轴的精确定位，微动开关将位置信号传给PLC主机；直流电机拖动手爪和底盘旋转，位置信号由旋转码盘和接近开关反馈给PLC主机；电磁阀控制气开阀的开关来控制机械手手爪的张合，从而实现机械手精确运动的功能。
Use computer to adopt the spectrophotometer signal, give continuous absorption in real-time. 3 Design a new and handy sample fraction collector, write the control module code. 4 Use computer to manager HSCCC system. By applying AD/DA interface technology and writing program, the system can measure HSCCC rotation speed, display the absorption curve in real-time, automatically collect the fraction.
对装置材质选择、装置散热方案及β值改变的方案做了讨论。2应用计算机采集紫外分光光度计信号，实现信号自动连续检测。3 设计和加工新型简便馏分收集仪，并编写其控制模块。4 高速逆流色谱系统的计算机管理。
Way reverse Dynamic Buffer 74LS240 as the dynamic scan segment LED code control drive signal, with P2.0-2.5 External 1 open-collector reverse gate 7406 to do the 6-bit selection signal drive LED mouth, 6 to 8 segment digital tube alignment were then 74LS240's output
以8路反向动态缓冲器74LS240作为LED的动态扫描的段码控制驱动信号，用P2.0—2.5外接一片集电极开路反向门电路7406做6位LED的位选信号驱动口，6个数码管的8根段选线分别接74LS240的输出，LED共阴极端与7406的输出端相连，从左到右依次来显示时，分，秒。
MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available
MAX1999EEI引脚说明：8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口，3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I/O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可
TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available
TDA4864引脚说明：8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口，3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I/O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可
Have priority in code circuit, latch, decipher circuit and export the input signal of the entrant team on the display; Starting the warning circuit with the control circuit and host's switch, two the abo..
优先编码电路、锁存器、译码电路将参赛队的输入信号在显示器上输出；用控制电路和主持人开关启动报警电路，以上两部分组成主体电路。
In chapter five, the base band signal process of CDMA base station simulator system is introduced, including channel coding and decoding, interleave and disinterleave, PN sequence generator, orthogonal spread spectrum and quadrature Spreading, scrambling code, power control, digital forming filter, the capture and track of PN code, dispreading and demodulation, etc. Some FPGA design graphic and waveform simulation of base band transmitter module is given and realization algorithm of base band receiver is discussed in detail.
第五章介绍了CDMA基站仿真系统的基带信号处理过程，包括信道编译码、交织与去交织、PN码发生器、正交扩频与四相扩频、扰码、功率控制、数字成形滤波器、PN码的捕获与跟踪、解扩与解调等，并给出了基带发射机模块的部分FPGA设计原理图和波形仿真，详细论述了基带接收机模块的实现算法。
A power control device for a mobile communication system includes a base station transmitter and a mobile station receiver, wherein the base station transmitter includes: a plurality of PCB pattern generators for multiplying PCBs for a plurality of mobile stations by user patterns assigned to the respective mobile stations, to generate PCB patterns for the respective mobile stations, wherein the user patterns are orthogonal with one another; an adder for adding up the PCB patterns from the plural PCB pattern generators to generate a power control signal; and a transmitter for modulating the power control signal received from the adder and transmitting the modulated power control signal, wherein the mobile station receiver includes: a power control signal extractor for extracting the power control signal within a given interval of a reception signal received on a single code channel, wherein PCB patterns for a plurality of mobile stations are added to the power control signal; a PCB pattern generator for multiplying the power control signal by the user pattern assigned to the mobile station itself, to extract the PCB pattern of the mobile station; and a decider for generating PCBs in accordance with a signal level of the extracted PCB pattern.
一种移动通信系统的功率控制装置，包括：基站发射机和移动台接收机，其中基站发射机包括：多个PCB模式发生器，用于将多个移动台的PCB与指定给各移动台的用户模式相乘，以产生各移动台的PCB模式，其中多个用户模式彼此正交；加法器，用于相加来自多个PCB模式发生器的PCB模式，以产生功率控制信号；和发射机，用于调制从加法器接收到的功率控制信号，并发送调制过的功率控制信号，其中该移动台接收机包括：功率控制信号提取器，用于在代码信道上接收到的接收信号的给定间隔中提取功率控制信号，其中多个移动台的PCB模式被加到该功率控制信号上；PCB模式发生器，用于将该功率控制信号与指定给移动台本身的用户模式相乘，以提取移动台的PCB模式；和判定器，用于根据所提取的PCB模式的信号电平来确定PCB。
The circuit designing that device happened in the function signal being that a kind of controls owing to ICL8038, module, AT89C52 monolithic machine under the control of module happened in wave form, lock appearance ring frequency division implement, keyboard, numerical code display, DAC0832 enlarge from precise function of ICL8038 composes capital.
本设计是一种基于ICL8038控制的函数信号发生装置，由ICL8038精密函数波形发生模块、AT89C52单片机控制模块、锁相环分频器、键盘、数码管显示器、DAC0832放大电路构成。
Wireless remote control codes encoded by the doorbell circuit transmitting and receiving signals of two parts, Remote encoding doorbell fired by the firing circuits and circuit switching code modulation circuit, Remote control signal sent by the remote code to receive doorbell circuit to receive remote control signals.
摘要无线编码遥控门铃电路由编码信号发射和接收两部分组成，遥控编码门铃发射电路由发射电路和开关调制编码电路组成，发出遥控信号，由编码遥控门铃接收电路接收遥控信号。
Some practical VHDL source code, a variety of signal modulation, there is the LCD control. taximeters, etc. source.
一些实用的VHDL源码，有各种信号调制的，还有LCD控制的，出租车计价器等等源码。
According to system functional requests and hardware design, it has been accomplished working software using system software architectures of digital signal processor, including AT command, PDU code, communication protocol, one-chip computer control procedure and explaining of SMS develop interface.
同时，根据系统功能需要和硬件设计方案，完成了系统的软件设计，包括AT指令、PDU编码、通信协议、单片机控制程序和短信开发接口说明，并给出部分软件流程图和子程序。
This paper introduces a circuit design plan of protecting motor winding coil against ultra warm by dealing with the ultra temperature protective signals from motor winding coil measured by sample sensor and utilizing pulse code technology of code hopping and remote control technology of the signal carrier.
本文介绍一种防止电动机绕组线圈超温的保护电路设计方案，该方案是通过电路处理温度取样传感器检测到的电动机绕组保护极限温度信号，利用滚动码脉冲编码技术、载波遥控技术实现的。
The encoding unit, composed of instruction buffer and command encoder, translates the 12-bit command code to 16-bit control signal, and ensures each part of the system to work steadily.
译码单元由指令缓存器和指令译码器构成，针对12位的指令代码翻译成16位控制信号，传送给处理器内部各个部件，用以保证各部件正常工作。
It adopts the digital code signal to control the gear changing and the states of the electric switch.
电子选发器采用数码信号控制换档和电子开关选通，从而克服了机械选发器的弊端。