Aggravated gate-induced drain leakage current was thought to arise from the higher induced electric field by the introduction of high-κ films, and field-emission current would be the dominant leakage mechanism.
我们认为高介电薄膜所产生的较高电场是引发严重的闸极诱发汲集漏电流的原因，而场发射电流为其主要的漏电流机制。
These TFTs are better than their solid phase crystallized counterparts in many process and device performance measures, such as shorter and simpler process flow, higher field effect mobility, reduced leakage current, better immunity to early drain breakdown and much improved spatial uniformity of device parameters.
低温金属单向诱导横向晶化多晶硅薄膜晶体管技术与常规的固相晶化多晶硅薄膜晶体管相比，制作工艺简单，而且提高了场效应迁移率和漏极击穿电压，降低了漏电电流，改进了器件参数空间分布的均匀性。
At the same time more than in 5 times is reduced current leak from the source to the drain, ie is reduced the energy consumption of transistor.
在同一时间，多在5倍，是减少泄漏电流，从源头上向外流，即是减少了能源消耗的晶体管。
In this topology, the main switches are operated under ZVS due to commutation of the transformer magnetizing current and the parasitic drain-source capacitance.
在此转换器，其主要开关主要是利用变压器的激磁电流和开关本身内部的寄生电容的换向，使得主开关操作於零电压的模式底下。
The leakage current of poly-Si TFTs is owing to the high drain electric field and large trap state density at drain junction. In this thesis, we found the silicon nitride film as the diffusion barrier prevents the hydrogen atoms downward diffusion and accumulated at the channel to further reduce the trap state density.
对於复晶矽薄膜电晶体其漏电主要与缺陷密度和集极电场强度有关，在本篇论文中我们发现氮化矽绝缘层能够有效的阻挡氢原子向下扩散而累积在通道之中，更进一步的去修补通道中的缺陷。
In this thesis, we used Si3N4 as the insulator of bottom-gated TFTs to investigate the effects of nitrogen and hydrogen radicals accumulated within the channel by NH3 plasma treatment. A reduction of the leakage current was observed because of effectively defect reduction in the drain junction.
在本论文中，我们使用氮化矽(Si3N4)当作底部闸极之绝缘层，探讨经氨气电浆处理后氢原子与氮原子能够累积在电晶体的通道内之效应，如此可进一步在汲极接面中填补通道的缺陷数量，可更有效降低元件漏电流之情形。
Accordingly, a higher forward current and a much improvement on drain saturation current could be achieved.
因此，较高的顺偏电流和较好的汲极饱和电流可以被达成。
It is shown that the electron drift velocity decreases rapidly and the drain current decreases linearly when increasing gate length.
随着栅长尺寸的增加，栅下沟道的电子漂移速度减小，而且漏电流呈线性递减。
The low quiescent drain current of the device insures good regulation when this method is used.
当这个方法被使用时，设备的低的静止的排水管电流保险好规则。
This paper puts forward an improved Curtice model, by modify drain-source current I ds and breakout volage V p of GaAs MESFET tube on the basis of Curtice semiexpirical model, and uses fast simulated annealing algorithm to resolve it.
从模型的建立方法来看，现有GaAsMESFET非线性模型大致分为 3种类型：(1)最值模型[1] 这种模型从求解GaAsMESFET的二维或三维电磁场方程出发，用数值计算算出MESFET的非线性特性。
The body effect of PMOS transistors was used to do further temperature compensation. The power supply reject ratio was improved by adopting the cascode and feedback structure. The proposed design exploited the relationship among the threshold voltage, the electron's mobility and the MOS's source-drain current in the subthreshold regime to reduce the impact of process variation to the reference current.
利用PMOS管的体效应实现进一步的温度补偿；利用共源共栅和反馈结构有效地增加了基准电流源德电源抑制比；并利用当工艺发生偏差时CMOS管阈值电压、电子迁移率和亚阈值区MOS管漏源电流之间的关系，降低了工艺涨落对基准电流的影响。
In unipolar transistors the terminals are source, gate and drain and the current flow is by majority carrier only.
在单极型晶体管中，引接端叫作源极、栅极和漏极，其电流是由多数载流子产生的。
The source-to-drain tunneling current is included based on the ballistic transport model in this work, using WKB method to calculate the possibility of tunneling. The device performances of DG MOSFETs with very thin silicon films (thickness of 1nm) are simulated.
2在经典弹道输运模型中引入源漏隧穿（ S/D tunneling ），采用 WKB 方法计算载流子源漏隧穿几率，对薄硅层（硅层厚度为1nm ） DG MOSFETs 的器件特性进行了模拟。
Carrier distribution and source drain current in subthreshold region were calculated in both semi-classical and quantum mechanical theories.
计算结果表明：在高掺杂浓度衬底时，量子化效应导致载流子浓度和亚阈区电流的显著降低和开启电压的升高，而对亚阈区斜率因子没有明显的影响。
Dependence of the normal current and supercurrent in the generalized two fluid model on gate voltage, drain voltage, temperature and frequency was analyzed.
分别对推广的二流体模型中正常电流和超导电流在一定的条件下随栅电压、漏电压、温度和频率的变化进行了分析。
In Chapter 4, we proposed a model for correlating the strain-induced low-field channel mobility gain, linear drain current gain, and saturation drain current gain in terms of the S/D resistance, the channel resistance, the ballistic efficiency, and the reduction of S/D resistance.
第四章里，我们提出一模型，此模型以源汲极寄生电阻、通道电阻、弹道传输率与寄生电阻的变化量等四个参数将制程引致的低电场通道迁移率增益、线性区与饱和区汲极电流增益关联起来。
It is demonstrated for the first time that the linear and saturation drain current gains can be modeled as linear functions of channel mobility gain with the intercept of S/D resistance reduction, where the S/D-to-channel resistance ratio and the ballistic efficiency determine the translating efficiency of channel mobility gain to the linear and saturation drain current gains, respectively.
此模型揭露出线性区、饱和区的汲极电流增益可表示为迁移率增益的线性函数，其截距大小与寄生电阻的变化量、源汲极电阻对通道电阻的比率有关。其中源汲极电阻对通道电阻的比率、弹道传输率分别决定著制程引致的迁移率增益对线性区、饱和区汲极电流增益的转换效率。
By utilizing the temperature power-dependence of drain current, we can deduce an analytic expression for extracting the channel backscattering ratio and related factors, and then analyze and discuss the mechanism responsible for strain-induced backscattering factor modulation.
载子传输方面，我们先以通道背向散射观点来检验通道应力对高横向电场下载子传输的影响。藉由背向散射参数与温度的指数关系，我们可得一简单的数学表示式以萃取通道背向散射系数与相关参数，讨论这些参数的变化对汲极电流的作用，并且分析何种机制造成应力引致背向散射参数的变化。
It is based on the exact surface potential solution of Poisson's equation and Pao-Sah's dual integral without the charge-sheet approximation, allowing the SRG-MOSFET characteristics to be adequately described by a single set of the analytic drain current equation in terms of the surface potential evaluated at the source and drain ends.
该模型基于泊松方程的精确的表面电势的解以及Pao-Sah的双积分模型，没有做薄层电荷近似，可以用一组用源端和漏端表面电势表达的解析漏电流方程描述环栅MOSFET 的特性。
Fig. 23 Spectrum of the drain current as shown in Fig.
漏极电流主要原理产生的电磁干扰频谱见图25。