After considering the via effect and heat fringing effect of multilevel ULSI interconnects, LTem provides more accurate temperature estimation of the multilevel interconnects.
模拟结果表明，考虑了通孔效应以及边缘效应之后，金属连线上的温度分布情况有了较大程度上的降低，LTem 可以得到更贴近实际情况的金属连线温度分布情况。
A-C:F film is an important kind of low dielectric material used in ULSI (ultra-large scale integrated) circuit. Its thermal stability temperature is required to meet the demand of damascene process (400℃). However, there exists a negative constrained relationship between the low dielectric constant and fine thermal stability of a-C:F film. Therefore, how to improve its thermal stability while keeping its low dielectric constant becomes a focus nowadays.
氟化非晶碳薄膜是用于超大规模集成电路的一种重要的低介电常数材料，作为电介质薄膜其热稳定温度必须达到平面工艺的温度要求(400℃)，氟化非晶碳薄膜的低介电常数和高热稳定性之间存在一种相互制约关系，如何保证a-C∶F薄膜介电常数相对较低的同时尽量提高其热稳定性成了目前倍受关注的课题。
With feature size reaching beyond submicron, the increase in propagation delay, crosstalk noise, and power dissipation of the interconnect structure become limiting factors for ULSI of integrated circuits.
当特征尺寸减小到亚微米时由此引起的信号延迟，窜扰，及功耗的升高，将成为限制大规模集成电路发展的主要原因。
Chemical-mechanical polishing is widely used in planarization of silicon substrate and multilayer metal interconnection construction and becomes one of core technologies in ULSI fabrication.
在集成电路制造中，化学机械抛光技术在单晶硅衬底和多层金属互连结构的层间全局平坦化方面得到了广泛应用，成为制造主流芯片的关键技术之一。
In this paper, we present a novel analytical thermal model for estimating the temperature rise of multilevel ULSI interconnects, and investigate in detail the impact of joule heating, Via effect and heat fringing effect.
本文详细研究了金属连线上的焦耳热对连线温度的影响，进而提出了一种新型的集成电路多层金属连线上的温度模拟器。该模拟器采用一种相对简单的热学解析模型，详细考虑了通孔效应以及边缘效应对温度分布的影响。
There are many procedures involve cleaning step such as oxidization, extension, diffusion, photofabrication and global complanation in the fabrication sequence of ULSI. The most time of cleaning is 80 times.
在ULSI的制备过程中，氧化、外延、扩散、光刻以及多层布线的全局平面化等工序都要涉及到去除污染物的清洗，清洗最多可以达到80多次。
The poor mechanical strength and interfacial adhesion of low-k film limit its application in modern ultra-large scaled integrated circuit (ULSI) fabrication.
low-k薄膜较差的机械强度和界面粘附性限制了其在ULSI制造工艺过程中的应用。
Research of WN film as diffusion barrier layer in ULSI-Cu metallization
集成电路亚45nm级铜布线扩散阻挡层WN薄膜的研究
Study and Optimization of CMP Slurry Used to Tantalum Barrier Layer of Copper Interconnection in ULSI
ULSI铜多层布线中钽阻挡层CMP抛光液的研究与优化
Analysis and Research on the Surface Roughness of the Copper Multilayer Interconnection CMP in ULSI
ULSI中多层Cu布线CMP表面粗糙度的分析和研究
Along with the fast development of ultra large scale integrated circuit (ULSI), the manipulation of impurities and defects in the CZ silicon crystal has been increasingly stringent.
随着超大集成规模电路的发展，半导体产业界已经把研究的重点放在了如何控制和利用硅中的杂质和缺陷上，即所谓的缺陷工程。
Chemomechanical polishing (CMP) technology of silicon substrate inULSI is introduced in this paper.
介绍了特大规模集成电路（ULSI）硅衬底的化学机械抛光工艺。
The development of ultra large-scale integrated (ULSI) circuit requires large diameter and defect free Czochralski (CZ) silicon wafers, which challenges the traditional crystal growth process and the 1C processing of silicon crystal.
集成电路的快速发展，要求硅单晶大直径、无缺陷，这对硅单晶晶体的生长、加工工艺及后继的集成电路工艺提出了全新的挑战。
Recent progress of multiple-valued logic and fuzzy logic research is analyzed with the focus on the applications of multiple-valued logic and fuzzy logic to soft computing, VLSI and ULSI, universal logic machine, design and test automation of digital systems.
分析了多值逻辑与模糊逻辑研究的最新进展，并着重介绍了多值逻辑与模糊逻辑在软计算、VLSI及ULSI、通用逻辑机及数字系统的设计与测试自动化方面的应用；
The interlayer dielectric materials with ultra low dielectric constant are researched to adapt to the development of the high speed and high density for ultra large scale integrated circuit (ULSI).
为了适应ULSI高速、高集成度发展，人们开始探索具有超低介电常数的电互联介质材料。
Preparation and properties of SiCN diffusion barrier film for Cu interconnect in ULSI
SiCN扩散阻挡层薄膜的制备及特性研究
Hot spot is one of the most important factors to the performance and reliability of ULSI.
1引言随着ULSI的发展，通孔产生的自热成了集成电路中一个非常重要的热源。
Dishing problem of copper multilayer interconnection in ULSI was introduced, and the reasons and influencing factors were analyzed.
介绍了ULSI多层铜互连线中的碟形坑问题，对其产生的原因及影响因素进行了分析。
Chemical-mechanical polishing (CMP) is widely used in planarization of silicon substrate and multilayer metal interconnection construction and becomes one of core technologies in ULSI fabrication.
在集成电路（IC）制造中，化学机械抛光（CMP）技术在单晶硅衬底和多层金属互连结构的层间全局平坦化方面得到了广泛应用，成为制造主流芯片的关键技术之一。
CMP Study of Multilayer Wiring Conductor Copper in ULSI Manufacturing
ULSI制备中多层布线导体铜的抛光液与抛光技术的研究