The paper introduces the hardware structure of CAN Bus intelligent adapter using advantages of high dependability and Real-time control of CAN bus, and adopting SJA1000 as CAN control chip, FIFO twin port RAM and PCA82C250 as interface chip of CAN controller designed for long-distance and strong interference special environment of mine monitoring.
针对矿井监控中距离远和干扰性强的特殊环境，利用CAN总线高可靠性和实时控制的优点，采用SJA1000作为CAN控制芯片，使用了FIFO型双端口存储器，并使用PCA82C250作为CAN控制器接口芯片，设计了CAN总线智能适配卡的硬件结构。
The hardware debugging of the Space Process module circuit has been completed with success. All the modules implemented in FPGA have been proved correct by software simulation and test. The design of the schedule submodule can offer some useful references in how to share a data path between multi-ports. The asynchrony FIFO module can be applied in the other asynchrony interface circuit design in multi-clock system.
本文中介绍的空域处理板的硬件电路已经调试成功，基于FPGA设计的数据接口模块和数据处理模块也都已经通过了时序仿真和验证；文中介绍的控制调度模块的设计对于多端口复用一条传输路径的电路设计具有一定的参考价值；异步FIFO的设计方案对于多时钟系统中异步接口电路的设计具有一定的参考价值。
It can be applied to t ho se systems which need to t ransmit or acquire mass data quickly by U SB Keywords:U SB 210; pattern of Slave FIFO; FP GA; high speed interface 210 interface.
该系统模块主要由 U SB 固件程序和 FP GA 控制软件组成，可应用到需要通过 U SB 21 0 接口进行高速数据传输或采集系统中。
Thirdly, the thesis describes the architecture of ethernet network interface modular-Ether-I/O Processor, including FIFO based input/output channel, multi-task microcontroller, and search machine which can do wire speed L2/L3 lookup. Fourthly, a performance analysis of Ether-I/O Processor is provided. Furthermore, the architecture of gigabit ethernet network interface modular-GbE-I/O Processor is briefly introduced.
接下来，通过对以太网I/O处理机（Ether-I/O Processor）的内部结构、处理流程、基于先进先出缓冲机制的输入/输出通道、多任务微控制器以及具有网络第二层和第三层线速地址查找功能的查询机器的介绍，分析了路由交换机的另一重要组成部分—以太网接口模块的设计原理，并对以太网接口模块的性能进行了分析；此外，还简要介绍了千兆以太网接口模块的结构。
Introducing the performance and data transmission characteristic of PCI 9054 interface chip, a realization method of FPGA based on PCI 9054 expanding asynchronous FIFO is put forward.
介绍了 PCI 9054接口芯片的性能及数据传输特点，提出了一种基于 PCI 9054外扩异步 FIFO的 FPGA实现方法。
As an example, let's write tests for a FIFO queue class named Queue, which has the following interface
我们将命名为Queue的FIFO队列类编写测试作为一个例子，Queue具有下面的接口
After that, this paper deeply analyses the conversion sequence of A/D device AD7899 and the principle of the hardware design which uses two methods to complete the data transfer between the interface of GPIF and the asynchronous FIFO storage. During the software design section, the thoughts of the software program are explained from four aspects. Firstly, in order to corporate with peripherylogic circuit and realize high date transfer rate, firmware is completed. Secondly, this paper discusses the device driver programs.
在软件设计方面，主要从四个方面阐述了该系统软件编程思想：一是配合外围逻辑电路实现最大传输速率和运行效率的固件程序编程；二是主机设备驱动程序和固件下载驱动程序；三是以动态链接库形式封装的方便用户再开发的功能函数和作为数据采集卡演示的主机应用程序；四是作频谱分析使用的软件系统。
It uses the asynchronous FIFO to interface between clock systems inside FPGA, and there is no need to shake hand with the other clock system.
用这样一个异步FIFO模块实现FPGA内部不同时钟系统之间的数据接口，它们之间不需要互相握手，只需跟接口FIFO模块进行交互就可以了，使设计变得非常简单和容易。
USB peripheral device chips are involved with FIFO and FIFO controller, Direct Memory Access Controller, Serial Interface Engine, USB2.0 Transceiver Macrocell Interface, and etc. These designed peripheral devices chip codes need be validated on developing USB2.0 IP core, which can be completed by self-designed UTMI codes. But this validating process will become very complex because self-designed UTMI codes are not always correct. In this paper, a set of detailed methods, which make use of utmi_fz Flexmodel in the SmartModel tools, and additional tasks to design a test validation system about USB2.0 Transceiver Macrocell Interface are presented. Simulation results show these methods are valid, so can offer a kind of reference method for developing USB2.0 system.
USB外设包括FIFO及FIFO控制器、IDE硬盘、直接存储器存取控制器、串行接口引擎、UTMI收发器、内存、微处理器单元等部分，在USB2.0 IP核开发时需要对设计的这些外设代码进行测试验证，测试时可以用自己设计的UTMI电路代码，但因其本身正确性还未加验证，因此测试较麻烦复杂，，本文通过实践给出了在开发USB2.0系统时利用utmi_fz FlexModel模型和自编task完成对USB功能块在事务层上各项作业通讯测试的方法和过程，仿真实践证明此方法是有效的，因此可为USB2.0IP核的设计开发提供参考帮助。
The hardware circuit includes ultrasonic excitation emission circuit, ultrasonic amplitude limiting circuit, ultrasonic amplifying and filtering circuit, detection circuit, A/D circuit, FIFO circuit, SCM control circuit and interface circuit.
硬件电路主要包括超声激励发射电路、超声限幅电路、超声放大滤波电路、超声检波电路、A/D电路、FIFO电路、单片机控制电路以及接口电路。
FIFO Data Interface Between Clock Systems Inside FPGA
FPGA内部时钟系统间的FIFO数据接口
As a slave device, the IP core includes AXI interface, two non-symmetrical FIFO, DMA interface and AES encryption core.
AES核做为SoC系统中的从设备，整个IP核包含了AXI接口，两个非对称FIFO与DMA接口，以及AES加解密核。
Realization of FPGA Expanding FIFO Based on the Interface Chip of PCI
基于PCI接口芯片外扩FIFO的FPGA实现
In the paper, we especially introduced the hardware architecture, signal conditioning, A/D conversion, FIFO circuit, USB interface circuit and EZ-USB firmware, application program and driver. It has extensive application foreground.
该文对系统硬件结构、信号调理、A/D转换、FIFO缓存和USB接口电路，以及EZ-USB的固件程序、PC端的应用程序和USB设备驱动程序进行了阐述，具有广阔的应用前景。
The scheme is based on ARM and FPGA with high-speed AD and FIFO, in which the interface to virtual instruments is implemented with USB, the interface to intelligent instruments implemented with graphic LCD, and the virtual interface implemented with Delphi.
该方案基于ARM和FPGA，配合高速AD和FIFO，以USB实现虚拟仪器接口，以图形液晶LCD实现智能方式仪器界面，用Delphi实现虚拟界面。
The peripheral controller consists of frequency detector, data sample controller, FIFO, LCD driver and the interface circuit between DSP and FPGA.
外围控制器囊括了硬件系统中几乎所有的数字电路，包括频率/周期测量、数据采集控制、FIFO、LCD驱动以及FPGA与DSP之间的接口电路等。
The hardware is made up by the signal conditioning circuits, the A/D converting module, the FIFO buffering circuits, the PCI interface, the FPGA control circuits and peripheral circuits.
硬件部分主要由信号预处理电路，A／D转换模块、FIFO缓存电路，PCI总线接口电路，FPGA控制电路及外围电路组成。
The asynchrony FIFO module can be applied in the other asynchrony interface circuit design in multi-clock system.
异步FIFO的设计方案对于多时钟系统中异步接口电路的设计具有一定的参考价值。
This paper introduced parallel communication methods of multiple monolithic computers with shared FIFO components. Here, the design of parallel communication interface of multiple monolithic computers system that use inquiry and interrupt method is mainly presented.
共用FIFO器件的多单片机系统并行通信方法，主要介绍采用查询方式和中断方式的多单片机系统并行通信接口设计。
In practice, this paper gives a detailed design implementation of various UART modules including reciever/transmitter, baud-rate generator, synchronous FIFO (First In First Out), Modem control module, interface module.
在具体实现上，本文给出了UART的各个模块的详细设计，包括：发送器、接收器、波特率发生器、同步先进先出缓存（FIFO：FirstinFirstout）、Modem控制模块、接口模块。