In the study diagnosis, we dig out the diameter of nozzle is small, or the thickness of nozzle space is thick, or the surface of spraying sheet is anti-water. Any of these factors make the ejecting droplet shrinking, let abridgement of time to the ejecting droplet come off the water cylinder, and abatement Clock Multiplier affection of ejecting droplet. Abatement appearance unevenness affection of ejecting droplet and speed.
经由实验结果，本实验发现当喷孔直径越小，喷孔片的厚度越厚，喷孔片的内表面呈现疏水性，上面任一条件皆可使喷出的液滴缩小，液珠脱离液柱的时间缩短，并且液珠不会因为倍频的振幅干扰，而出现喷出的液珠体积不均匀或是速度不均匀的现象。
In order to realize this method, a new kind of high speed and high precision digital phase-locked frequency multiplier is designed and realized.
利用这种分析方法，对下述几个工程实际问题进行了必要的探讨。1）。
In the digital signal processing, multiplier's speed has the important influence to the entire chip as well as the system performance.
在数字信号处理中，乘法器的速度对整个芯片以及系统性能有着重要的影响。
After doing that, the paper points out the universal architectures of the high-speed real-time signal processing system and describes how to implement them.. Since FFT plays an important role in digital signal processing, implementing FFT with FPGA is presented and the total realization graph is designed. For improving speed and decreasing computing complexity, high efficiency multiplier algorithm is used to realizing twiddle factor multiplier of butterfly processing unit.
最后本文描述了数字信号处理系统结构的实现方法，指出常见的高速、实时信号处理系统的四种结构；由于FFT算法在数字信号处理中占有重要的地位，所以本文提出了用FPGA实现FFT的一种设计思想，给出了总体实现框图：重点设计实现了FFT算法中的蝶形处理单元，采用了一种高效乘法器算法设计实现了蝶形处理单元中的旋转因子乘法器，从而提高了蝶形处理器的运算速度，降低了运算复杂度。
Due to high integration and high speed operation, array multiplier much likely suffers from delay fault.
摘要阵列乘法器因高度集成和高速运行，容易受到时延故障的困扰。
The multiplier used to improve the Booth algorithm, simplified some of the plot symbols expansion Wallace tree and used-ahead adder circuit to further enhance the computing speed.
该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。
In the design of JPEG coder, the modified Loeffler FDCT algorithm is applied, the problem of time parallel is resolved with pipeline optimization structure, and the speed of DCT module is accelerated. The design of CSD algorithm-based fast multiplier is seasoned with the DCT pipeline structure. Implement the Huffman coder with LUT mode, according to the orderliness of Huffman coding table, using less store unit.
在JPEG编码器设计中，采用改进的Loeffler快速离散余弦变换算法，用流水线结构解决时间并行性问题，提高了离散余弦变换模块的运算速度；设计了基于CSD编码的高速乘法器以适应离散余弦变换模块流水线设计的要求；用查表方式完成了霍夫曼编码模块，依据霍夫曼编码表的规律性，用较少的存储单元完成霍夫曼编码的运算。
System level features - SelectRAM+ hierarchical memory: 16 bits/LUT distributed RAM Configurable 4K-bit true dual-port block RAM Fast interfaces to external RAM - Fully 3.3V PCI compliant to 64 bits at 66 MHz and CardBus compliant - Low-power segmented routing architecture - Full readback ability for verification/observability - Dedicated carry logic for high-speed arithmetic - Efficient multiplier support - Cascade chain for wide-input functions - Abundant registers/latches with enable, set, reset - Four dedicated DLLs for advanced clock control - Four primary low-skew global clock distribution nets - IEEE 1149.1 compatible boundary scan logic Versatile I/O and packaging - Low cost packages available in all densities - Family footprint compatibility in common packages - 19 high-performance interface standards, including LVDS and LVPECL - Up to 120 differential I/O pairs that can be input, output, or bidirectional - Zero hold time simplifies system timing Fully supported by powerful Xilinx ISE development system - Fully automatic mapping, placement, and routing - Integrated with design entry and verification tools
系统级功能- SelectRAM +分层内存：16位/ LUT的分布式RAM配置4K的位真双端口RAM块快速接口，外部RAM -全3.3V的PCI兼容的64位66 MHz和；的CardBus标准-低功耗分段的路由架构-读回能力进行全面核查/观-携带专用高速算术逻辑-高效乘法器支持-宽输入功能级联链-/与启用，设置，复位锁存寄存器丰富-四个专用DLL的先进时钟控制-四小学低偏移时钟分布全球网技术- IEEE 1149.1边界扫描逻辑兼容通用的I/O和封装-低成本封装密度在所有可用的-家庭中常见的包足迹指数- 19高高性能接口标准，包括LVDS和LVPECL差分I高达120 -/ O对，可以输入，输出或双向-零时间，简化了系统定时举办全强大的赛灵思ISE开发系统的支持-全自动映射，安置和路由-综合与设计输入和验证工具
In practice, fast adders such as CLA adder is always used in the last stage of CSA array multiplier to increase its speed.
在实际电路中，为了提高乘法的速度，CSA（Carry-SaveAdder）阵列乘法器的最后一级常采用CLA加法器等快速加法器。
This multiplier-adder unit is based on CSD coding and adopts both 3-2 compressor and Wallace tree, its multiply-add operation is realized by entire parallel approach, and Three-Greedy connection algorithm is applied to this unit to improve its speed.
该常数乘加器基于CSD编码技术，采用3-2压缩器，并以华莱士树为其基本结构，以全并行算法来实现其乘加运算，且采取了先进的Three-Greedy连线算法来优化此乘加结构的速度。
The data input order is rearranged, and a high speed constant multiplier is designed and implemented. The whole design is developed to apply VHDL to a 1.0 μm COMS library and syntheticlly.
根据算法安排了数据的输入顺序，设计了数据通路、高速的常数乘法器、控制电路，用VHDL语言完成了整个设计并进行了仿真和在1.0 μm COMS库上的综合，电路面积约为3 400等效门。
In this paper, from the point of error control, potential maximum errors are analyzed and calculated in the execution of two different fixed-point multiplication methods. One is to retain the low half portion, the other is to retain the high half portion. Analysis is based on an error model of isolated fixed-point multiplication and the features of fast DCT algorithm, of which one of the multiplier is constant. Conclusions thus obtained are applicable to data scaling and precision allocation, and are useful in the determination of the best alternative among several satisfactory fast speed DCT algorithms.
本文结合快速DCT运算中乘法运算的某些特点，在单个定点乘法误差模型基础上，从控制运算结果的最大误差角度，就分别保留乘法结果的低半部分和高半部分两种不同的定点乘法结果处理方法，对定点DCT运算的最大误差情况进行分析，以指导前述两个问题的解决。
You can also use it for drive benchmarking, easily comparing speeds through'X'speed multiplier factor, in real conditions.
您也可以使用它为基准的驱动器，速度比较容易通过的' X '的速度倍数，在现实的条件。
Deals 200 bonus damage (not part of the crit multiplier) and Decreases move speed by 45%.
并且减少百分之四十五的移动速度。
The paper presents a multiplier circuit based on Booth algorithm when the radix equals four by studying the Booth algorithm. The carry-save-array adder and the pipeline technique are drawn into the design for improving the circuit speed.
通过对Booth算法的研究，本文提出了一种基4Booth算法的硬件乘法器电路，为了提高硬件乘法器电路的运算速度，将保留进位加法电路和流水线技术引入了该乘法器电路。
Secondly, systolic array Multiplier is designed which can speed up the multiplication of two matrices.
其次本文设计了脉动矩阵乘法器，用于加快两个矩阵的乘法运算。
It is shown that this scheme has a higher speed and a small delay than the traditional CSA array multiplier.
优化下的并行乘法器比传统的CSA阵列乘法器速度快，且延时小。
Array multiplier is one of the high_speed multipliers used in the high_speed computers, such as PENTIUM. This paper discusses the design and operation rules of the complement array multiplier.
阵列乘法器是在PENTIUM等高速计算机中采用的一种高速乘法运算器，据此讨论其补码阵列乘法器的设计和运算规则。
Secondly, put forward a new kind of digital serial pulse structure, based on the structure designed series-parallel mixed modular multiplier, which achieved best matching on both speed and area.
其次，提出了一种新型数字串行脉冲阵列结构，设计了基于此结构的串并混合模乘器，在速度和面积上达到了最佳匹配。
Introduces a new type programmable self-adaptive digital frequency multiplier. Comparing with traditional analog and digital frequency multipliers, it has the advantages of high tracking speed, high phase accuracy, and wide frequency range.
介绍了一种新型可编程自适应数字频率倍频器，与传统的模拟和数字倍频器相比，它具有跟踪速度快、相位精度高和频率范围宽等优点。