This experiment adopts rats model with right middle cerebral arterial ischemia, by means of rolling training, balance training and Morris training, to observe the differentiation ability of mice in false operation group, rehabilitation group by rehabilitation training and model group without being trained, and to observe the action pattern of the ability to reflect memory maintenance by one passive avoidance reaction, and the memony of rats with brain infracted by rehabilitation training and its mechanism by means of the LTP record, the NMDA receptor channel record and the measurement of synaptic structure parameter of hippocampus CA3 area.
为此本实验采用右侧大脑中动脉缺血大鼠模型应用滚笼网状训练、平衡训练以及Morris水密宫训练后，观察假手术组、经康复训练的康复组和未经训练的模型组大鼠在Y-迷宫分辨学习能力和一次性被动回避反应记忆保持能力的行为模式以及海马CA3区突触结构参数测定、在体LTP记录和NMDA受体通道电流记录等方法研究康复训练对梗死大鼠学习记忆的影响及其机制。
Memory screen is the step number. Pressingdown the fixture channel list, but the step
如果需要，一个编程过的记忆可以给一个名字。
Clear up the doubts: ddr memory dram array in the channel and data transmission between the logic of a particular component, this is called dqs pulse generated by the components making memory data signal output and external clock synchronization signal.
释疑：ddr内存在dram阵列和数据传输通道之间有一个特殊的逻辑部件，这个叫dqs的部件产生的脉冲信号使得内存数据输出与外部时钟信号同步。
The invention discloses a direct memory access device, comprising bus Slave interface, DMA request and response interface, bus Master interface, control logic and register set, channel logic and register set, and interrupt request logic, where the key point is that control logic of each DMA channel in the channel logic and register set comprises: channel control logic used to control state switching of first and second state selection units and control read-in/-out of data from source address to destination address; first and second data buffer areas for storing data read in DMA channels in different directions; first and second state selection units for reading data from the source address into the first or second data buffer area and sending data in the second or first data buffer area to the destination address.
本发明公开了一种直接存储器存取装置，包括总线Slave接口、DMA请求和响应接口、总线Master接口、控制逻辑和寄存器组、通道逻辑和寄存器组、中断请求逻辑，关键是，通道逻辑和寄存器组中每个DMA通道的控制逻辑包括：通道控制逻辑，用于控制第一和第二状态选择单元的状态切换，并控制数据从源地址到DMA通道到目的地址的读入和读出；第一和第二数据缓冲区，存储不同方向读入DMA通道的数据；第一和第二状态选择单元，将来自源地址的数据读入第一或第二数据缓冲区，并将第二或第一数据缓冲区的数据发往目的地址。
The main circuit structure、chips for central control choosing、input channel of simulation amount design and A/D sampling of the system are compared, choice-making methods and design principle for function modular such as reference pulse adjusting、clock circuit、communication modular、data memory、keyboard circuit and liquid crystal circuit presented in the paper.
论文中对系统的主体电路结构、主控芯片的选择、模拟量输入通道设计和A/D采样方法进行了详细的方案比较和论证；并给出了基准脉冲整形、时钟电路、通讯模块、数据存储器、按键电路和液晶电路等功能模块的电路原理图。
It includes an on-board non-volatile memory for storage of critical information such as module identifier, channel setup, transducer calibration data, etc.
它内含一块板载的非易失存储器用作储存重要信息，如模块标示符，通道设置，传感器校准数据等。
There are two general types of these coprocessors:programmed I/O channel and direct memory access.
协处理器有两大类型：程序控制I/O通道和直接存储器存取。
OUTPUT IMPEDANCE CONTROL In order to put all streams in three-state, all per-channel three-state control bits in the Connection Memory are set (MOD0 and MOD1 = 1) or both the ODE pin and the OSB bit of the Control Register must be zero.
输出阻抗控制为了使所有流在三态，在连接所有内存每通道三态控制位设置（MOD0和MOD1 = 1）或两者的管脚和常微分方程的控制位定向结构刨花板注册必须为零。
In particular, as a non-volatile memory device undergoes many programming cycles, charge becomes trapped in the insulator or dielectric between the floating gate and the channel region.
特定来说，在非易失性存储器装置经历许多编程循环时，电荷变为俘获在浮动栅极与沟道区之间的绝缘体或电介质中。
The main concept of this dissertation provides a new method to probe the change of the surface potential along the channel in a small area SONOS type memory. It is accomplished by combining the extraction of the trap position with the random telegraph signal resulted from the interface trap located in the bottom oxide.
本篇论文主要提供了一个新的方法来探测小面积SONOS快闪记忆体沿著通道的表面电位变化，这个新方法是藉由结合缺陷位置萃取技术和底层二氧化矽缺陷所产生的随机电报杂讯来达成。
The memory capacity is 288 devices per channel and total memory capacity scales with DRAM bit density.
的内存容量是288器件，每通道的存储容量和总表与DRAM位元密度。
We use the synergetics to study how to allocate input probability in the binary symmetric discrete channel in order to maximize average mutual information for memoryless and memory channels with interference.
在有干扰无记忆信道和有记忆信道两种情况下，运用协同学的方法研究如何分配输入概率获取二元对称离散信道最大的平均互信息。
Mandatory memory good a high advertisement effect of the media all the bus passengers is a relatively closed travel carriers, passenger information is basically in a vacuum, buses on the best movie player can not only bring joy to the travelers, the lifting of long-distance travel of the boring and fatigue, but no switch-board television channel ratings up to 100%, auditory and visual are mandatory, memory depth, the best ads.
强制记忆性广告效果佳高客传媒的所有客车是个相对封闭的远行运输工具，乘客基本处于信息真空状态，客车上播放的精彩电影不仅能够给旅客带来欢乐，解除长途旅行的枯燥和疲劳，而且车载电视不设切换频道，收视率可达100%，听觉和视觉均属于强制性，记忆深刻，广告效果最佳。
In this example embodiment, the graphics processor has sole use of both graphics local memory channel 1 and graphics local memory channel 2 (as shown with the cross-hatched locations 0 to x for both channels).
在这个示例实施例中，图形处理器具有刘`图形本地存储器通道1以及图形本地存储器通道2(如对于两个通道采用交叉阴影线的位置0到x表示)的单独使用权。
The background music is one of my music creations named Memory, if you like it, you can listen to it in my site or Buy it from itune store, please visit my channel profile for more infomation.
背景音乐是我的创作曲：回忆，如果喜欢的话欢迎到我的网站聆听和下载，如果想要下载高品质的音乐档，可以到itune store购买或是寄信告诉我喔！
The product includes the following features: high-precision stepper regulator (each step 0.0144 ul higher chemical compatibility (using ceramic and fluorocarbon fluid constitute channel high load cycle (tested up to 84 million cycles electronic controller easy to learn and master; memory 100 work procedures; Supporting foot switch and remote control; to support independent operation and panel installation; support system integration, instrument integration and multi-distribution.
的产品包括以下特性：高精度步进调节（每步0.0144 UL）的，更高的化学兼容性（采用陶瓷和碳氟化合物构成流体通道）；高负载周期（经测试达到84万次），电子控制器易于学习和掌握，记忆100个工作程序；支持脚踏开关和遥控，支持独立运行和面板安装；支持系统集成，仪表集成和多分布。
Both the traditional EEPROM and the flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate.
传统的EEPROM和快闪存储器两者均利用半导体衬底中定位于沟道区上方且与其绝缘的浮动栅极。
In this work, we fabricated and characterized n-channel floating-gate and silicon-oxide-nitride-oxide-silicon flash non-volatile memory devices.
在本研究中，我们制作和描述n 型通道的悬浮闸与SONOS非挥发性快闪记忆体元件特性。
He had never heard any music of the city, but a decade of super-memory and the channel control skills is his greatest guarantee. He absorbed mass amount of the Chinese and foreign songs of well-known singers, listened to the songs at the daytime and performance at night. And even be able to sing while listening to the songs. He has sung exactly like the original voice of the famous singers.
他从没听过城市里的任何音乐，但十几年练成的超强记忆力和对声道的控制是他最大的保证，他海量地吸收着中外所有知名歌手的所有歌曲，白天所听，晚上即演，甚至现学现唱，原音重现，与歌手本人的演唱声音并无一丝一毫的差别。
The second drawback can be addressed by making the system memory channel peak bandwidth greater than half that of the graphics memory channel peak bandwidth.
可通过使系统存储器通道的峰值带宽大于图形存储器通道的峰值带宽的一半，来解决第二个缺点。