The key manufacture technologies include selecting right material, designing the device structure, epitaxial growth of silicon, etching the gate of the device, forming the deep through and so on.
研究内容主要包括：静电感应晶闸管的材料选取、结构设计、关键制造技术外延以及台面刻蚀和深槽刻蚀等的研究。
Prepatterned ITO pads served as the gate regions; Silicon nitride layer was deposited by a plasma enhanced chemical vapor deposition, and then the gate dielectric was defined by photolithography and etching; Indium oxide was deposited as an active layer by RF magnatron sputtering at room temperature. Aluminum was deposited as sourse and drain electrodes by evaporation method.
本文利用光刻工艺，成功制作出氧化铟薄膜晶体管，器件采用底栅式结构，以ITO玻璃为衬底，腐蚀出TTFT栅电极，采用PECVD法沉积氮化硅，通过光刻和腐蚀工艺获得绝缘层，室温下磁控溅射氧化铟作为TTFT有源层，热蒸发方法沉积铝膜作为源漏电极。
The selective etching solution is applied to the fabrication of undoped-GaAs/n-GaAs modulation-doped channel MISFET. The MISFET exhibits excellent and reliable performance, demonstrating the applicability of this solution to gate recess process.
利用这种选择腐蚀技术制备了undoped-GaAs/n-GaAs调制掺杂沟道金属-绝缘体-半导体场效应晶体管，获得了很好的器件特性参数，证明了这种腐蚀溶液适合于器件制备中的栅挖槽工艺。
With 8 wafers per batch, the etching uniformities on a wafer and of wafer-to-wafer are below ± 5%, At present, this technology has been used in our development and manufacture of silicon gate MOS ICs.
每批8个3吋园片，其单片和片间均匀性可达±5%以下。目前我们已将该技术用于所有的硅栅MOS电路的研制之中。
Started with silicon wafer our TFFEC processes consist of wet isotropic chemical etching for cone formation, oxidation and etching for tip sharpening and self-aligned gate process.
我们用硅材料为基体，用各向同性的湿法化学腐蚀工艺制出尖端，用氧化增尖和自对准栅极工艺制成TFFEC&薄膜场发射阴极。
To cut off connecting department of gate-cathode (or source) electrode formed in the epilayer processing, and to open the electrode area, we used the mesa etching.
为了切断栅极和源极（或阴极）之间在外延过程中形成的连体，打开栅电极区，进行了外延后的台面刻蚀，对台面刻蚀的深度和形状进行了研究；
Measurement and analysis results show that the serious effect of etching process on the surface of SiC is the cause of inferior quality of gate oxide which strongly depresses the control of gate voltage on the channel.
对测试结果的分析说明：由于刻蚀对SiC造成的表面损伤严重影响了栅氧化层的质量，导致栅电压的控制能力很弱。
The selective etching solution is applied to the fabrication of undoped-GaAs / n-GaAs modulation-doped channel MISFET. The MISFET exhibits excellent and reliable performance, demonstrating the applicability of this solution to gate recess process.
利用这种选择腐蚀技术制备了undoped-GaAs/n-GaAs调制掺杂沟道金属-绝缘体-半导体场效应晶体管，获得了很好的器件特性参数，证明了这种腐蚀溶液适合于器件制备中的栅挖槽工艺。
In addition, we found that etching the gate and then etching the deep through can fabricate good devices easier than etching the deep through and then etching the gate.
另外，对先刻蚀台面还是先刻蚀槽的问题给出了实验对比结果，结果发现先刻蚀台面在现有实验条件下有利于器件特性的改善。