An external signal is necessary in the locking process of the traditional multiplying delay-locked loop. It is used to set total delay of the cyclic delay line in acquisition range of the phase detector, or the whole loop would be out of control. The output clock range of the clock synthesizer using cyclic pulse generation technique is limited by the acquisition range of the PD, and the clock synthesizer could not change its output clock frequency from low to high.
传统的倍数延迟锁定回路(Multiplying Delay-Locked Loop，MDLL)的锁定行为，必须先利用一个外部重置讯号将全部延迟调整到最小延迟，再逐渐增加延迟来锁定回路，这是为了避免循环式延迟线所产生的全部延迟超过了相位侦测器的有效捕捉范围，使延迟锁定回路的负回授机制无法回复至其近似锁定状态，因此产生的时脉无法由低操作频率转换至高操作频率，且输出频率范围受到限制。