MICROPROCESSOR 微处理器Usually a single integrated circuit on a chip; Logic circuitry of
通常指一个芯片内的单一的完整的电路；微型计算机的逻辑电路；和microcomputer 同义。
The circuit under test may be asynchronous. The basic logic unit may be gate-level or function-level unit. Besides, the algorithm is capable of self-initialization.
被测时序线路可以是异步的，基本逻辑单元可以是门级或功能级元件，此外，算法具有自初始化的能力。
In the analysis of combinational logic circuit, should take into account gate delay time of the impact on the circuit.
在分析组合数字逻辑电路时，应该考虑门电路的延迟时间对电路产生的影响。
Introduction of digital circuit in the combinational logic circuit, individuals think quite good.
详细说明：介绍数字电路中的组合逻辑电路，个人认为挺不错的。
A special-purpose optical transmitter, an optical receiver and a programmable logic device are used to design system circuit to realize asynchronous multiplexing fiber optic transmisson of multiway serial interface signal with different baud rate.
该系统采用可编程逻辑器件结合专用光电发送和光电接收器进行设计，实现了不同速率的多路串口信号复用的光纤传输。
Line may be out or open line somewhere, or may have a logic gate circuit fault.
可能是列线或行线某处断路，或者可能是逻辑门电路产生故障。
This paper is focused on the FPGA internal logic design ideas and methods in the transmitting and receiving circuit board which composes the whole transmission system: The control implementation which includes the digital video decoder chip on the transmitting board, SRAM and the fiber physical layer transmission chip; The operation of asynchronous clock domain, display of the image restructuring and the coding technology design; image decoding in the receiving board`s FPGA, district display technology and the 24-bits parallel pixel data`s serial transmission designing.
论文着重介绍了组成整个传输系统的发送与接收电路板上FPGA内部的逻辑设计思想与设计方法：发送板上FPGA对数字视频解码芯片、片外SRAM以及光纤物理层传输芯片的控制实现，异步时钟域操作、显示图像重组与编码技术设计；接收板内FPGA的图像解码、分区显示技术以及24bit并行象素数据的串行传输方案实现。
It is still another object to provide a dual frequency radar system using a logic circuit requiring no manual selection.
它仍然是另一个对象提供双频雷达系统使用逻辑电路无需手动选择。
Programmable logic devices; counter; digital circuit; VHDL
可编程器件；计数器；数字电路； VHDL
We can change the electric circuit of the existing machine tools using PLC and also can substitute the logic circuit, which has complicated circuit connection and poor reliability in intrinsic machine tools using the powerful logical operation power of PC.
其工作过程是通过CPU的周期扫描并采用集中采样、集中输出的方式来完成的；继而对格栅清污机控制电路(包括主电路、控制电路、信号及照明电路)进行分析。
GAL16V8D is employed to deal with the BLDCM rotor position signals and the other logic signals. The BLDCM drive circuit is mainly composed by Three-Phase Full Bridge Inverter and gate driven IC IR2130 with its peripheral circuit. A three loop control strategy, with current loop as the inner one, braking moment loop as the outer one, and slip ratio loop as the outermost one, is applied here.
论文详尽地阐述了以TMS3320F240为核心的控制器硬件构成，充分地利用DSP内部资源并辅以外围电路构成了速度检测、电流反馈、过流保护、串口通信等功能电路，利用GAL16V8D实现无刷直流电机的转子位置信号等逻辑信号的处理，以IR2130为中心构成了三相全桥电路实现无刷直流电机的高效驱动。
When the output of the integrator crosses the reference voltage (5V), the comparator trips, activating the clocked logic circuit.
当积分器输出交叉参考电压（5V），比较考察，激活时钟的逻辑电路。
Based on an analysis of the timer structure on the C54x, a new design scheme of an adiabatic timer is presented using the theory of three essential circuit elements for adiabatic circuits and the characteristics of the clocked transmission gate adiabatic logic circuit and its adiabatic flipflop.
为了设计低功耗定时器，首先利用钟控传输门绝热逻辑电路设计绝热触发器，然后在分析C54X的定时器结构基础上，利用绝热电路三要素理论，结合钟控传输门绝热逻辑电路及其绝热触发器的特性，提出绝热定时器的设计新方案。
This research is to design a simple logic content state analyzer circuit.
本文研究内容是设计一个简易逻辑状态分析仪电路。
In our approach, an In-Circuit Emulator unit is added based on IEEE 1149.1 standard and some modifications on control logic are made, which enables SuperV2 support debugging operations such as setting breakpoints, single-step execution, accessing the registers and memory inside the processor, etc.
本文基于IEEE 1149.1标准，针对SuperV2微处理器的体系结构，在其内部实现在线仿真（In-Circuit Emulator，ICE）单元，并对SuperV2的部分控制逻辑做相应改动，使得修改后的SuperV2微处理器能支持预设断点、单步执行以及访问处理器内部寄存器和存储单元的调试操作。
Considering strict and complex phase requirement, phase locked loop was used for precise phase shifting. Through Embedded logic analyzer the timing was sampled and verified. The driving timing generator of CCD camera with adjustable integral time was implemented on the CCD circuit board.
考虑到CCD驱动时序复杂、相位要求严格，提出运用锁相环技术进行高频信号的精确移相，用嵌入式逻辑分析仪对时序进行采样验证，在CCD电路板上实现了积分时间可调的CCD空间相机驱动时序。
Considering strict and complex phase requirement, phase locked loop was used for precise phase shifting. Through Embedded logic analyzer the timing was sampled and verified. The driving timing generator of CCD camera with adjustable integral time was implemented on the CCD circuit board. Frame transfer CCD; Integral time; Phase locked loop; Embedded logic analyzer
考虑到CCD驱动时序复杂、相位要求严格，提出运用锁相环技术进行高频信号的精确移相，用嵌入式逻辑分析仪对时序进行采样验证，在CCD电路板上实现了积分时间可调的CCD空间相机驱动时序。
Binary LOGIC CIRCUIT ry, on the other hand, has ONLY two states, LOGIC 0 and LOGIC 1, and noire immunity of hundreds or thousands of millvolts.
另一方面，二进制逻辑电路只有两个稳态——逻辑0和逻辑1，其噪声容限可以达到数百至数千毫伏。
For example, consider the following logic diagram of a circuit
中：举例来说，考虑接下来的这个逻辑电路
LOGIC DIAGRAM, A diagram that uses logic gates to represent the function of a control circuit.
逻辑电路示意图，一个用逻辑门来示意控制线路功能的图。