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电源
...2V 基准电压的精度可达VCC UVLO门限值,VCC输入欠压锁定(UVLO) 电路禁止(图6),DL_ 同步整流驱动器则直接由外部5V电源(VDD)电容(CISS - CRSS) 以及电路板寄生电容引起的LX_和DL_当V CC升至约2V时,...
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电源 电源
...REF)与电源电源(VDD)关系曲线(VTHREF)与热敏电阻偏置电流(ITHREF)关系图2-22: 电源电流(ISS)与环境温度图2-23: 电池调节电压(VBAT)与环图2-31: 充电电流(IOUT)与编程电阻(RPROG)关系曲线图2-32: 充电电流(IOUT)与环境温输入电源电压应高于欠压锁定(UVLO)阈值电压,...
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电源正端
...一旦功率开关Q1闭合,电感器就会与电源正端(VDD)相连,流经电感器的电流开始呈线性迅速上升. 当PWM信号达到高电平时,功率开关Q1就会断开,此时,电流流经二极管D,来维持电流回路....
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内部(低压)电源
...该电流可由内部低压电源(VDD)来提供. 由于VDD提供的最大电流被内部保护电路限制在11mA,因此,为了防止电流供应不足,设计时应附加一个辅助低压电源. UBA2032的同类器件还有U-BA2030和UBA2033等....
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abbr. visual device driver program; 虚拟设备驱动程序
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abbr. visual device driver; 虚拟设备驱动
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abbr. velocity of diastolic depolarization; 相自动去极速度
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abbr. version description document; 版本说明文件
A resistor to VDD and a capacitor to ground from the MONO IN terminal enables the one-shot circuit and controls its pulse width.
一个到VDD的电阻和在终端单声道到地电容使一杆电路和控制其脉冲宽度。
In the area of pacemaker implantation, our department has carried out VVI, VDD, AAI、DDD, DDDR, anti-atrial fibrillation pacemaker implantation, and implanted cardiac defibrilator and Bi-Ventricular pacing device implantation.
在起搏器植入方面，开展了VVI、VDD、AAI、DDD、DDDR及抗心房颤动起搏器，还开展了埋藏式心脏除颤起搏器及双心室起搏器的植入。
The experimental results show that the buck/ buck-boost converter works well with the following features: the maximum inductor current up to 750mA; the input voltage range is 3~6V; the output voltage range from 0.45 to input voltage-0.4V; the maximum power efficiency up to 93.6%.
在降压/降升压转换器正常工作范围内所实测结果：最大电感电流750mA；输入电压范围3~6V；输出电压范围0.45V~(VDD-0.4)V；最大效率可达到93.6%。
11All dynamic characteristics use VDD = 5 V. 12Different from settling time after fuses are blown.
11All动态特性使用VDD的5五12Different从解决保险丝时间=后吹。
The frequency of the scan oscillator is determined by an external capacitor between VSS or VDD and scan input.
扫描的振荡器是由一个与VSS或VDD和扫描输入外部电容决定频率。
The common mode range of the TI+ and TIC pins is from 1.2 V to VDD C 1.2 V. This is an FET gate input.
这是TI +和议会引脚的共模范围是从1.2 V至VDD的 1.2五，这是一个场效应晶体管栅极输入。
Bypass VDDP with 0.1 F and 0.001 F capacitors to GNDP.
采用0.1 F和0.001 F电容将VDD旁路至GND。
AIM:To assess the value of VDD pacing to improve symptoms and release left ventricular outflow obstruction in patiens with obstructive hypertrophic cardiomyopathy.
潘迪华 ，陈建中，阳跃忠，黄文新目的：探讨VDD起搏器治疗肥厚性梗阻型心肌病的临床疗效及其血液动力学变化。
MC145554P Pinout: RFR6000 Device Features · Compatibility with QUALCOMM's radioOne ZIF chipset eliminates the entire IF, reducing component count and space · Single- or multiband operation: cellular, PCS, GPS · Single- or multimode operation: cellular CDMA, PCS CDMA and GPS · Full downconversion RF to baseband · Receive path circuitry C GPS LNA C Stepped gain control C Three sets of quadrature downconverters C Band-specific low-pass filter C Baseband amplifiers with DC offset adjustment · Only one single-band external VCO is needed for all CDMA bands of operation for entire radioOne chipset · Includes entire on-chip GPS VCO-including resonant circuit · Individual circuit power on/off controls · Power reduction feature control extends handset standby time C Selective circuit power-down C Gain and bias controls · Low-power supply voltage (2.7 to 3.0 V), low-power dissipation C Digital reference voltage is compatible with lower MSM voltage (1.8 to 3.0 Vdd)· Available in small, thermally efficient package 40-pin BCC
MC145554P引脚说明：RFR6000设备特点·与高通公司的芯片组的radioOne的ZIF兼容性省去了中频全，减少元件数量和空间·单或波段操作：蜂窝电话，个人通讯，全球定位系统·单或多模操作：蜂窝CDMA及PCS CDMA和GPS ·全变频射频到基带接收通道电路直流· GPS LNA与步进增益控制C三组的正交下变频器C波段专用低通滤波器基带放大器失调调整·只一单波段外部VCO的运作都需要对整个的radioOne所有CDMA芯片组·包括整个频带上的芯片GPS的VCO，谐振电路·个人，包括开/关控制·节电功能扩展电路的功率控制手机的待机时间C选择性电路断电C增益和偏置控制·低电源电压（2.7至3.0 V），低功耗C数字参考电压与低电压兼容的MSM（ 1.8至3.0电压Vdd）·提供小，热效率的封装
In addition, each well needs at least one well tap to ensure the well is at the proper electrical potential (taps to Vdd for the n-wells in the process you are using).
为了减少面积，单位电路里的井会延伸至电路边界，以致连接后各单元变成在同一个位井里。
Excessive current will flow if input is brought below VDD 0.3 V.
过量的电流流入如果低于VDD的投入带来了-- 0.3五三。
Due to the debounce circuitry on the RESET input, VDD must be applied for at least 31.2 ms.
由于在复位输入去抖电路，VDD的申请必须至少在31.2毫秒。
Parameter RESOLUTION Offset Error Gain Error Differential Nonlinearity Integral Nonlinearity TEMPERATURE DRIFT Offset Error Gain Error POWER SUPPLY REJECTION RATIO ANALOG INPUTS1 Differential Input Voltage Range Differential Input Resistance Differential Input Capacitance Input Bandwidth VSWR 2 POWER SUPPLY 3 Supply Current IAVCC (AVCC = 5.0 V) IEVCC (EVCC = 3.3 V) IVDD (VDD = 3.3 V) Total Power Dissipation 4
参数解决方案偏移误差增益误差微分非线性积分非线性温度漂移偏移误差增益误差电源抑制比1模拟输入；差分输入电压范围差分输入电阻电容输入带宽差分输入电压驻波比2电源3电源电流IAVCC（AVCC = 5.0五）IEVCC（EVCC = 3.3伏） IVDD（VDD的= 3.3伏）总功率耗散4
A selective SOI structure having body contacts for all the devices while excluding the buried oxide that is directly underneath diffusions of DC nodes such as applied voltage Vdd, ground GND, reference voltage Vref, and other like DC nodes is provided.
一种选择性绝缘体上硅结构，该结构具有用于所有器件的体接触，而不包含直接地位于直流节点扩散区下面的埋置氧化物。
It should be noted that in the quiescent state CX is fully charged to VDD, causing the current through resistor RX to be zero.
应当说明的是，在静态的时候，CX已经充电完毕，通过它的电流变为零。
In this configuration, this pin has an open-drain output that requires an external 5-k pullup resistor connected to VDD.
在此配置中，该引脚有一个开漏输出，需要一个外部的5kΩ的上拉电阻连接到VDD。
Otherwise, VDD2 connects to VDD directly if double pump option is enabled.
否则，VDD2连接到VDD直接如果双泵选项已启用。
No external ramp components needed s Built-in over-voltage and under-voltage detection s High-speed over-current trip; 170 ns typical s Over-voltage clamp on supply voltage s Internal divider regulates VDD to 12 V. No external divider needed s Leading edge blanking of the current sense signal s Control frequency modulated over a narrow band to reduce Electromagnetic Interference s High output drive capability; 150 ns typical rise and fall time into 2 nF load s Wide bandwidth (10 MHz) error amplier with external compensation pin and simple interface to optocoupler s Accurate internal bandgap reference.
无需外部元件坡道需要的内置过电压和欠电压检测的高高速过电流跳闸； 170纳秒典型的S过电压钳位电压之内部分隔VDD的12个五，没有规定外部分压器需要的主导优势的电流感应信号的消隐法控制频率超过1窄带调制，以降低电磁干扰的高输出驱动能力； 150纳秒典型的上升和下降到2 nF的负载时间s宽带宽（ 10兆赫）错误与外部补偿引脚和简单的界面，光耦放大器到精准农业内部带隙基准。
The ADC is designed to dynamically optimize the QT burst length according to the rate of charge buildup on Cs, which in turn depends on the values of Cs, Cx, and Vdd.
ADC的动态优化设计的QT间期突发长度根据铯收费率，从而对铯，国泰航空，和VDD值取决于建设。
TPS65120RGTR Pinout: Two-level OCP with 96mS delay time Peak-current-mode operation with cycle-by-cycle current limiting PWM frequency continuously decreasing w/ burst mode at light loads Low start-up current (8uA) Low operating current (3.7mA) VDD over-voltage protection AC input brownout protection with hysteresis Programmable over-temperature protection Constant power limit over universal AC input range Internal latch circuit for OTP, OVP, OCP Very few external components
TPS65120RGTR引脚说明：双水平96mS延迟时间与逐周期峰值电流模式工作电流限制PWM频率不断下降开路电位低启动电流轻负载瓦特/突发模式（8uA）低工作电流（3.7毫安）VDD的多电压保护AC输入滞后欠压保护可编程过温保护对通用AC输入范围内为恒功率限制锁存检察官办公室，过压保护，开路电位非常少的外部元件电路